The present invention relates to a method and/or architecture for Delay Locked Loops (DLLs) generally and, more particularly, to a method and architecture for a self-clocking a digital controlled Delay Locked Loop (DLL).
Some applications can require that data be valid within a precise time from a clock edge. The clock to data valid (tco) time and the data output hold time (tdoh) dictate the data valid window. Also, the duty cycle of the data can be required to follow the duty cycle of the clock so that the data valid window is not reduced. A zero delay buffer that tracks the clock jitter and duty cycle can be used to meet the requirements.
A conventional zero delay buffer that tracks the clock jitter and duty cycle can include a Delay Locked Loop (DLL). The DLL can generate a phase-adjusted version of an input clock such that a desired edge (e.g., rising or falling) of the DLL clock occurs a time tco before a corresponding edge of the input clock. The phase-adjusted clock can be used to clock data out of a chip so that the data to input clock time is ideally zero.
The DLL is a closed loop system that adjusts the propagation through a delay line such that the delay is equal to the clock period minus the clock to output delay. A phase detector and filter adjust the delay line until a feedback clock is delayed 360 degrees (i.e., phase aligned) with respect to the input clock. Since the compensation delay can be set equal to the time tco, the delay line can have a delay equal to the clock period minus the time tco.
Referring to FIG. 1, a block diagram of a circuit 10 is shown illustrating a digital DLL. The circuit 10 includes a phase detector 12, a digital delay line 14, a compensation delay 16 and a digital loop filter 18. Every cycle the DLL 10 makes an adjustment with the phase detector 12 and filter 18 that corresponds to a phase adjustment in the delay line 14. One of the difficulties of designing a digital DLL is deciding how to clock the synchronous circuits. The digital loop filter 18 requires a clock to synchronously update the position of the delay line 14.
Referring to FIG. 2, a timing diagram 20 is shown illustrating various phases of the signal Input Clock propagating down the delay line 14 to generate the signal DLL_CLOCK. Because of the various clock phases in the delay line 14, guaranteeing that a clock edge will not be skipped or the duty cycle will not be corrupted is difficult. Two alternative approaches are used for clocking the digital filter 18 to update the delay line 14. The digital filter 18 can use the signal Input Clock (or a delayed version) or the signal DLL_CLOCK from an output of the delay line 14.
Referring to FIG. 3, a block diagrams of a circuit 10xe2x80x2 is shown. The signal Input Clock can be used to clock the digital loop filter 18xe2x80x2 to update the delay line 14. Whether the loop filter 18xe2x80x2 is a counter, a shift register or a multiplexer tree, the signal Input Clock must update the delay line 14 such that none of the edges propagating down the delay line are changed. For long delay lines or low frequency there is more time to make the update. However, for high frequencies or short delay lines, multiple clock edges may be propagating down the delay line 14 and the timing is difficult to guarantee.
Referring to FIG. 4, a block diagram of a circuit 10xe2x80x3 is shown. The circuit 10xe2x80x3 is similar to the circuit 10 except that the loop filter 18xe2x80x3 is clocked by the output clock DLL_CLOCK. The circuit 10xe2x80x3 has the same difficulty as the circuit 10xe2x80x2 at high frequencies since multiple clock edges can be propagating down the delay line 14. One approach for minimizing the timing constraint is to update only the end of the delay line 14. By updating only the end of the delay line 14, other edges earlier in the delay line will not be affected by the update and the critical time is the output clock edge until the next clock edge. However, the time from the output clock until the delay line is updated must be less than the duty cycle.
The disadvantage of the conventional approaches is that there is a timing constraint on the clocking of the digital loop filter 18 that can result in the DLL 10 missing edges or changing the duty cycle. The timing constraint reduces the maximum frequency of operation of the DLL 10.
It would be desirable to have a clocking scheme for a digital delay locked loop that minimizes the timing for updating the delay line.
The present invention concerns an apparatus comprising a delay line and a control circuit. The delay line may be configured to generate an output signal in response to an input signal and one or more control signals. The delay line may be self-clocked. A phase of the output signal may be adjusted in response to the one or more control signals. The control circuit may be configured to generate the one or more control signals in response to the input signal and the output signal.
The objects, features and advantages of the present invention include providing a digital delay locked loop that may (i) use a synchronous digital control to update the delay line position, (ii) have a delay line comprising multiple stages, (iii) have stages that propagate an output to a next stage and to a synchronous control circuit, (iv) have a self-clocking delay line, and/or (v) be used in applications that need a zero delay buffer including memory chips that need a small clock to output delay.